An algorithm may be employed to limit a number of substrates in an electronic device manufacturing tool during electronic device manufacturing (e.g., flat panel display and/or semiconductor device manufacturing). One conventional algorithm considers a number of slots corresponding to service chambers (e.g., load lock chambers, heating chambers, etc.) included in the electronic device manufacturing tool and a customer-specific offset, which is based on the customer's electronic device manufacturing tool topology. Such an algorithm does not adapt to a change in the electronic device manufacturing tool configuration, for example, due to a processing chamber fault during electronic device manufacturing. Consequently, such an algorithm may not efficiently limit the number of substrates in an electronic device manufacturing tool during electronic device manufacturing. As a result, dead locks and/or bottlenecks (e.g., jams), which adversely affect electronic device manufacturing throughput, may occur during electronic device manufacturing. Accordingly, methods and apparatus are desired for enhancing electronic device manufacturing throughput.